Fibre Channel networks are known loop configuration networks that have a plurality of known type nodes such as servers, printers, disk arrays etc. all connected together by the loop. Such networks use a unique protocol involving a plurality of 40 bit primitives that are used to arbitrate for loop control, to establish connections and to carry out flow control for data transfers of frames of data. The flow control inherent to the Fibre Channel Arbitrated Loop network (hereafter FCAL nets) protocol has the advantage of eliminating the need for the nodes to have extensive buffering capabilities since the destination node controls the amount of data it receives by transmission of an RRDY primitive to the source node each time the destination node is ready to: receive another frame.
Fibre Channel networks emerged as a family of interconnection topologies to increase bandwidth over fast-wide SCSI networks and to increase the number of server and storage elements that can be connected to 126 over the 16 device limit of SCSI. Advantages of FCAL include that devices may be farther apart (up to 10 km) and more numerous and that the size of data transfers is very large compared to the overhead that is required to set up every transfer. This makes FCAL very efficient and more attractive than less efficient protocols such as TCP/IP over Ethernet and SCSI over a bus connection.
Hub based network topologies are generally desirable because they overcome certain limitations on the number of nodes that can be coupled to a network by breaking it up into segments coupled by the hub. Many Ethernet networks use hubs as do token ring networks. Hubs in FCAL networks receive packets from a source node on an input line coupled to the source node and rebroadcast the packet on an output line coupled to the next node which rebroadcasts the packet to the next node and so on. The rebroadcast by subsequent nodes in the chain wastes computing resources. Switched topologies work differently in that packets are not rebroadcast, but instead are connected directly to the line coupled to the destination node thereby eliminating processing by other nodes which are not the destination to receive and rebroadcast messages not destined for that node.
Despite their advantages, a significant problem in FCAL networks is delay and this delay increases as the network scales up in size. Each meter of cable contributes 5 ns of delay. Further, each node contains an elasticity buffer or FIFO to absorb the differences between incoming and outgoing data rates. Data passing through a node enroute to its destination passes through the nodes elasticity buffer and suffers a typical delay of 3 words. Typically, disk clusters are 10 drives to a cluster with each drive being one node and imposing its own delay. If there are 10 clusters coupled to a server, this would represent typically 5.3 microseconds of delay in transition of each primitive and data frame travelling around the loop. In other words, this delay is imposed on each loop tenancy. In an I/O operation, there are typically 4 tenancies for a write to disk, each involving 3 xe2x80x9cround tripsxe2x80x9d: ARB, OPN-RRDY and Data/CLS (see ANSI standard X3T10FCP which is hereby incorporated by reference). Thus, 12 delays would be suffered by each command transaction. On a 100 node loop, this translates to approximately 64 microseconds of delay per command.
xe2x80x9cThe command overhead of modem disk drives is around 200 microseconds and falling. The delay per command coupled to the command overhead of the drive imposes a significant penalty on performance of approximately 32%. For random access benchmarks with small I/O payloads typical of database queries, the performance penalty becomes more pronounced. The problem manifests itself as the inability of the server to achieve more I/O operations per second, regardless of how many more disk drives are added to the system.xe2x80x9d
Spatial reuse provided by switches or hubs which allow concurrent loop tenancies is one way of reducing the delay problem. The IBM serial storage architecture in the prior art is one method of providing spatial reuse.
Connection oriented switched topologies were tried in early Fibre Channel Fabric networks to attempt to overcome the delay problems of loops by cutting down the number of nodes each primitive and data frame passes through in getting from source to destination and providing spatial reuse. These early fabric switches were complicated, expensive and slow, all of these characteristics being found quite undesirable by artisans of FCAL networks. In the early FC Fabric switches, an entire frame of data with a header that indicated the destination node to which the frame was directed was sent to the switch for purposes of requesting a connection. These early switch designs had microprocessors which were used to implement several layers of software architecture to receive the frame, pass it up through various layers of processing to find the frame boundaries, crack the frame open, determine its destination address and then attempt to find the destination node and make the switching connection. The entire frame of data had to be buffered during this process of attempting to find the destination and make the proper connection. It was possible in this early design that the connection was never made, because, for example, the destination node was busy with another conversation. The switch would then have to send a message back to the source that no connection was made and to try again later. Because of limited buffer space in the switch, the data in the original frame might need to be overwritten by other data from a frame of data embodying another request. In such a case, the switch would have to send another message to the source saying, xe2x80x9cSorry, I lost your data. Execute error recovery protocol.xe2x80x9d Error recovery protocols further complicated the operation and construction of such systems. If a connection is made, the switch receives another frame of data back from the destination. This frame also must be received, have its boundaries detected and must be cracked open to examine its contents to see if the destination is saying, xe2x80x9cYes, I am available for a connection.xe2x80x9d This type of switch proved to be unworkable and FCAL loops became the standard interconnect for disks and servers.
Prior art Fibre Channel switches are commercially available from Ancor and Brocade Communications which provide spatial reuse and efficient link utilization. The FL_ports connected to these switches also address physical delays as they pertain to FCAL. However, these switches require link rate frame buffering to accomplish their performance levels, and also operate on the entire 24-bit address contained in the FC frame. In contrast, the invention described herein uses zero buffering and an 8-bit address decode for a much more efficient and inexpensive design.
Many network switched topologies that use entire frames of data to request a connection through the switch suffer these same drawbacks. The need for errory recovery protocols arise because of the potential for lost data arising from the fact that only limited amount of memory can be put in the switch at realistic costs, and in heavy traffic situations, the memory may be exhausted and some portion thereof may have to be rewritten with new data before the original data is delivered. Memory is expensive, takes up space and complicates the design.
Examples of other network topologies other than Fibre Channel Fabric that suffer these same drawbacks are the 1 Gigabit Ethernet(copyright) and ATM protocol networks now in public use.
The Fibre Channel Arbitrated Loop (FCAL) topology emerged as a way of providing simple, low-cost connectivity to more nodes over a shared media than could be provided in point-to-point topologies without the requirement for an expensive fabric switch. FCAL networks allow up to 126 node ports to be coupled by a shared media using a simple protocol without the need for a separate fabric switch. Unlike the switched fabric topology which has a centralized approach to routing, FCAL networks distribute the routing function to each loop port. This reduces the cost of achieving interconnection since the loop functionality represents a relatively small addition to the normal port functionality that has to be present anyway. However, FCAL networks suffer the disadvantage that the number of concurrent interconnections possible is smaller than in switched fabric networks because FCAL networks are fully blocking topologies such that only two pairs of nodes on the loop can communicate at any particular time. All other nodes have to wait until the first pair are done communicating before the loop is available for another pair to communicate. The address space is also limited to 126 nodes. Another problem with FCAL topologies is that traffic originating from a source node had to travel through each intermediary node on the loop portion between the source node and a destination node. Since each node imposed a delay, the overall bandwidth was decreased since each loop tenancy involved a protocol wherein OPN, RRDY and CLS primitives and data frames had to travel through all these intermediary nodes in order to complete the loop tenancy. Since no other pair of nodes could communicate until the loop tenancy was complete, the delays in transmission imposed by each node on each portion of the protocol decreased overall bandwidth and throughput.
In an attempt to further increase bandwidth and concurrency without the extremely high cost of fabric switches, combinations of FCAL loops with smaller fabric switches have been devised. This allows the cost per port of the fabric switch to be amortized over the total number of ports including those coupled to the subloops coupled to the switch.
The problem with the approach of coupling multiple FCAL loops together by a fabric switch is that each FCAL subloop must be coupled to the fabric switch by a complicated port called an FL_port. These are ports which must be able to understand the FCAL loop protocol on one side of the port and interface it with the very different and substantially more complex fabric switch packet switching protocol on the other side of the port while also having bridging functionality. Such FL_ports must have protocol layers that understand each protocol and can do packet routing and communicate with each other.
Further, FL_ports are expensive to build. This is because of the inordinate amount of buffer memory that is needed in the front end of the FL_port to reconstruct the sequences of packets contained in one FCAL tenancy. Modern day connectionless fabric switch protocols are pure packet switching while FCAL loop tenancy protocols are single conversations which tend to be like a simple switched circuit and contain many packets. That is, the FCAL loop tenancy protocol starts with an OPN primitive directed to a destination node which responds with an RRDY directed to the source. These primitives set up switches in the nodes so that the source and destination nodes talk directly to each other through the loop segment between them and the intervening nodes by sending one or more frames of data until a CLS primitive is sent which ends the conversation.
In contrast, the packet switching done by an FL_port on the switch backplane side is not nearly this simple. The packet switching protocol requires the FCAL frames output by a source node to be treated as many individual packets. Those packets must be routed to the correct destination FL_port and reassembled there without loss of data and launched on the FCAL loop on which the destination port is resident. Thus, FL_ports will receive packets from the fabric switch side and data frames and primitives from the FCAL loop side and must have the memory and intelligence to convert between the two protocols.
In the treatise Kemble, Arbitrated Loop, Chap. 1, pp. 18-19, FIG. 12, Published by Connectivity Solutions, Tucson, Ariz. (1996), ISBN 0-931836-824, Kemble proposes a xe2x80x9cSmart Hubxe2x80x9d conceptual network. This network is comprised of a plurality of FCAL loops coupled together by a smart hub which has the intelligence to provide independent operations within each loop. When a source node wants to exchange data with a destination node, it arbitrates for its local loop and attempts to establish a loop connection with the destination. If the destination is local, the smart hub simply acts as a repeater. If the destination port is not local, the smart hub intercepts the attempt to establish a loop connection, acquires access to the proper destination loop and establishes the loop connection between the source and destination loops acting like a bridge. Thus one loop can talk to another without affecting activity which is purely local to the other loops not involved in the connection, but the other loops cannot set up simultaneous connections to nodes on other loops during the tenancy across the smart hub of the first cross-boundary connection between the two loops already connected across the smart hub. This type arrangement cannot satisfy the need for a fast switch which is affordable and provides the ability for multiple pairs of ports to communicate simultaneously across the switch.
As a response to the limitations on concurrency present in conventional FCAL topologies, the assignees of the present invention devised a network topology using intelligent hubs each of which had routing intelligence and each of which had its own subloop coupled to a plurality of conventional L_port nodes of a type used in conventional FCAL topologies. Each hub was coupled to each other hub by a broadcast data path and a return data path. By watching the addresses in the OPN primitives and the flow of primitives, the hubs were able to deduce the location of the source and destination nodes and cut out all subloops and nodes thereon that were not necessary for communication between the source and destination nodes thereby decreasing unnecessary delay in completing each loop tenancy and increasing bandwidth. Further, some concurrency was supported in that tenancies between source and destination nodes on the same subloop could be completed simultaneously on each subloop, thereby further increasing throughput. This technology is described in U.S. Pat. No. 5,751,715 which is hereby incorporated by reference.
The assignee of the invention has also filed a co-pending patent application on a learning bridge for FCAL topologies such that two or more FCAL loops can be coupled together by bridges. The bridges have the intelligence to examine the destination addresses of OPN primitives received from their local loops and watch the primitives of loop tenancies and the loops from which they came and to learn the locations of various nodes on the loops to which they are coupled. Each bridge then forwards OPN primitives from one loop to another if the destination node is on a different loop than the source node, but keeps the OPN local to the same loop as the source is on using a local bypass data path if the destination and source nodes are on the same loop. This provides the ability for concurrent loop tenancies to be occurring on the two loops coupled to.the bridge, although only one loop tenancy per loop is allowed at any particular time. This technology is described in the parent application incorporated by reference herein.
Despite these improvements over standard FCAL topologies provided by the assignee, there is still a need for further improvements in concurrency without the increased cost and increased protocol complexity of fabric switches. What is needed is a way to achieve the high concurrency and bandwidth of fabric switch topologies without the high cost thereof. Therefore, a need has arisen for a relatively simple, FCAL switch which has little or no buffer memory needed therein and which is capable of establishing connections very fast. Fundamentally, what the prior art is missing is a switch which can couple multiple FCAL loops together with high concurrency and the speed of a fabric switch that uses N_ports and which couples FCAL loops together without the expense, complexity, memory demands and slowness of fabric switches that use FL_ports (FL_ports can support fast switching, but the amount of memory needed makes the cost prohibitive). This switch, in an ideal world, would have multiple ports, each of which is coupled to an FCAL loop or an NL node and provide concurrency such that each port can talk to any other port at any time the other port is not already tied up in another loop tenancy.
Two important attributes of all species within genus of the invention are: first, the use of the destination address in an FCAL OPN primitive (hereafter referred to as an OPN) instead of a frame header of a frame of data to find the destination node and establish the connection through the switch; and, second, using the normal flow control primitives of the FCAL protocol for hold back purposes to eliminate the need for large buffer memories in the switch and so as to implement a switching protocol to stream complete data frames from source to destination without storing any data frames in the switch, and without any packetizing, and without any segmentation and reassembly processing, and without any error recovery protocols to retransmit dropped frames. Any species that shares these two characteristics is within the preferred genus of the invention. This preferred genus qualifies for class 2 Fibre Channel operation where frames cannot be dropped because the flow control nature of the switch prevents frames from ever being dropped because they are only transmitted when the destination node has indicated it can receive them. The preferred genus can also be operated in class 3 Fibre Channel operation where it is permissible to drop frames and upper level protocols do error recovery for dropped frames even though the switch never drops frames.
A separate second genus of FCAL switches, suitable for Class 3 Fibre Channel operation only, still uses the destination address in the OPN to find the remote port but uses buffers instead of hold back flow control to complete the transaction to busy remote ports. Specifically, species within this genus will use the destination address of the OPN from the source node to find the location of the remote port. Then the status of that port will be checked. If the status is available, a connection request will cause a connection to be set up between the source node and the destination node via a source port connected to the source node and a destination port connected to the destination node. The buffer comes into play when the destination port is busy. In this situation, in the first genus described above, the normal primitives of the FCAL protocol are used for flow control to prevent the source node from transmitting any frames of data until the destination port becomes available. In the second genus defined in this paragraph, a buffer big enough to hold one or more complete frames of data is included in the front end of each switch chip, or multiple buffers each big enough to store a frame of data are included with each switch chip front end. Each of these buffers will serve as an auxiliary switch port and have its own connection to the backplane in some species or a single shared connection to the backplane through a multiplexer can be used. The preferred species uses multiple buffers each with its own connection to the backplane in addition to a connection directly from the switch port to the backplane for direct connections without buffering. In some species, a single shared buffer or multiple shared buffers on the backplane or in some central location may be used.
In this second genus, the way the buffers are used is for the source port to generate an RRDY sub sponte when it finds from a check of the scoreboard that the destination port is busy. The RRDY is sent to the source node and causes it to output a frame of data. This frame of data is stored in the switch port""s buffer. Then a message is sent to the destination port indicating that the auxiliary buffer of the switch port is holding a frame of data for the destination port. This auxiliary buffer ID is added to the camp list for the destination port. When the destination port becomes available, a message is sent back on the protocol bus indicating that the destination port is now available and naming the backplane channel to use. A connection through the backplane is then established to this channel by the auxiliary buffer connection circuitry and the destination port, and the data in the auxiliary buffer is transmitted. If the switch port has multiple auxiliary buffers, they each have their own IDs and, preferably, each has its own switching circuitry to make a connection to the backplane.
In this second genus, each auxiliary buffer has circuitry coupled to the return path to recognize RRDYs transmitted back by the destination node and to count them (or store them) and to wait for a connection between the source port and the RRDY counting circuit if the connection is not continuous such as in some cases where multiple buffers are present in each switch port. These stored RRDYs (or self generated in the case of a count only) can be transmitted to the source node in the case of full duplex or mixed with frames from a third node in the case of a dual simplex connection and transmitted to the source node. Each source port also has shared circuitry for each FCAL net which recognizes incoming RRDYs from the source node and counts them or stores them. These source node generated RRDYs can be transmitted to the destination node in the case of full duplex or transmitted to a third node in the case of dual simplex.
Returning to consideration of the first genus, the normal buffer by buffer accounting and the hold back, handshaking nature of the FCAL loop protocol with large data frames makes this genus of switches possible and also very efficient.
The FCAL OPN primitive is a small 40 bit quantity which includes a code indicating it is an OPN primitive and includes a destination address, and an optional source address if the OPN is full duplex. Receipt of the OPN starts the process carried out by the switch of finding the destination and causes establishment of the connection or a notification to the source that the connection could not be established before any data frame is ever transmitted to the switch. This lack of transmission of any large data frame before establishment of the connection means that the switching circuits connected to each FCAL loop coupled to the overall switch structure do not need to have buffer memories to store the data while the connection is being made or the fact that a connection is not possible is established. This allows for greatly simplified hardware. This means lower costs and greater density of ports per chip. This cost advantage is a significant improvement over prior art approaches.
The major subclass of embodiments taught herein uses a plurality of ports for connection to individual FCAL loops, and a crossbar switch which couples the ports together and which can implement any number of separate data transfer channels under control of the ports with the port using the destination address information in the OPN primitives to determine whether or not a connection through the backplane from one port to another is needed. In the preferred species, the ports are integrated circuits with many ports on one chip and a portion of a distributed crossbar switch also integrated on the chip to selectively couple the integrated circuit to one of the backplane data path channels. Each port is essentially a learning bridge front end with an interface to the crossbar switch on the backend.
Fairness is provided, in the preferred embodiment, by a fairness token which circulates to all the ports and which, when held by a particular port, gives that port xe2x80x9chigh priority statusxe2x80x9d. This means that if an OPN comes in to a port with the fairness token in its possession and the destination node is on a remote port, the high priority status of that port means that it can xe2x80x9ccampxe2x80x9d on the remote port and wait for it to be available and it is guaranteed access to the destination node no matter how busy it is. Since the fairness token circulates, no port will ever be starved from communication with a busy node.
Different variations or species within the subclass are taught. Distinctions between species within the subclass are based upon: the way the destination node is found; the way in which the first port coupled to the source node signals the second, remote port that there is traffic waiting for one of the NL nodes to which it is coupled; whether the crossbar switch is central or distributed; whether the complete routing table is stored in each port or there is a single separate routing table, or whether there are partial routing tables stored in each port; whether a scoreboard is used or not to determine the status of a remote node; and, if a scoreboard is used, whether it is distributed with a copy in each port or centralized and shared by all ports. All these variations between species and combinations of variations are equivalent to each other even though each has its own peculiar advantages and disadvantages.
As an example of variations between species within the inventive genus defined above consider the following. Location of the destination node can be by any of several means since the OPN includes the destination address therein. In one embodiment the destination address from the OPN is used to address a lookup table which outputs data as to which loop the destination node is on and to which switch chip or port coupled to the destination loop the switching connection should be made. This embodiment has the advantage that all the connection information is immediately available. This allows the connection to occur more rapidly. The disadvantage of this species is that the look up table is larger and each port must carry a full copy of the routing table.
One alternative embodiment uses a destination location process wherein the destination address of the OPN from the source node is used to address a lookup table (hereafter LUT) which only outputs a single bit indicating, in one logic state, that the destination node is xe2x80x9clocalxe2x80x9d, i.e., on the same FCAL network as the source node, or indicating, in the opposite logic state, that the destination node is not on the local loop. If the destination is not local, the destination address is broadcast as a location request to the other switch chips coupled to the other FCAL networks connected to the switch. Each of the other switch chips then checks its local LUT using the destination address to determine if it has the destination node on its loop. The switch chip that has the destination node finds this out from data returned from its local LUT and then sends a message to the switch chip coupled to the loop having the source node telling it, to where the connection is to be made and whether the connection can be made, i.e., the loop upon which the destination node is not busy in another conversation and is available for the connection. The advantage of this species is a smaller routing lookup table may be used in each port. The disadvantage is the requirement of more message traffic between chips resulting in slower response.
An example of an FCAL switch within the genus of the invention is a bufferless switch for coupling to a plurality of FCAL nets and having a crossbar switch and FCAL loop interface port circuits structured to use the OPN and RRDY primitives of the FCAL protocol for hold back flow control to eliminate the need for a buffer with the ports and crossbar switch structured to provide multiple simultaneous loop tenancies.
One embodiment for a protocol within the genus of protocols which define the rules to set up a connection through an FCAL switch within the genus of the invention between a source node and a destination node and transfer data therebetween is:
1) in a source node, arbitrating for and winning control of a first FCAL net and transmitting an OPN primitive thereon, the OPN primitive having a destination address of a destination node therein;
2) receiving and latching at a first port of an FCAL switch the OPN primitive from the source node coupled to the first port by the first FCAL net;
3) using the destination address in the OPN primitive as a search key to search a routing table to find the location of a destination node having the destination address in the OPN or the ID of a port coupled by an FCAL net to the destination node, or both, and, if the destination node is coupled to the first port, passing the OPN primitive to the destination node via the first port via a local bypass data path coupling an input of the first port to an output of the first port coupled to the first FCAL net, but, if the destination node is coupled to a second port other than the first port, controlling a crossbar switch to establish a data path between the first and second ports and determining if the second port is available, and, if so, sending the OPN primitive to the second port indicating traffic is waiting to be sent to said destination node and latching the OPN in said second port;
4) in the second node, arbitrating for control of a second FCAL net coupled to the second port;
5) when control of the second FCAL net is won following said arbitration, forwarding the OPN to the destination node;
6) receiving an RRDY primitive or a CLS primitive from the destination node in the second port and transmitting the primitive so received to the source node through a connection established across crossbar switch, and through the first port and the first FCAL net; and
7) for each RRDY received by the source node, transmitting a frame of data to the destination node through the first FCAL net, the first port, the data path through the crossbar switch, the second port and the second FCAL net without ever storing it in a buffer in the switch, and continuing to pass data frames and primitives between the source and destination nodes, until a CLS primitive is transmitted by either the source node or the destination node, and then closing the data path through the crossbar switch and relinquishing control of the first and second FCAL nets.
The preferred subclass of the switch utilizes the concepts of the learning bridge taught in the parent application incorporated by reference herein for front end circuitry coupled to the FCAL net with backend circuitry which is coupled to a crossbar switch. The bridging front end uses the destination address in the OPN to decide whether or not to connect the front end circuitry to the back end circuitry. The crossbar switch implements a plurality of completely separate data paths through the switch each of which can couple two ports together. The provision of multiple separate data paths through the crossbar switch eliminates any bottlenecks which could occur if a multiplexed data bus were to be substituted for the crossbar switch. It is within the genus of the invention however to substitute a multiplexed bus for the crossbar switch using any form of multiplexing.
Thus, the switch apparatus genus could be generally described as including multiple species, each comprised of a plurality of half bridges, each with a front end for connecting to an FCAL loop and a backend coupled to either a crossbar switch or a multiplexed bus along with suitable control circuitry to use the destination addresses in OPN primitives to determine whether a connection between two ports through the crossbar switch or multiplexed bus is necessary and, if necessary, for establishing the connection.
In the preferred embodiment, each half bridge is one port. In the preferred embodiment, the half bridges are implemented as integrated circuits with a multiplicity of half bridges on every chip with each half bridge building its own routing table by a passive learning process. An alternative embodiment uses an active discovery process to build the routing table.
The switch architecture can be thought of as a multi-port switch with a stack of learning half bridges substituted for each FL_port of a prior art fabric switch, with each half bridge on each layer being coupled to its own local FCAL loop or single NL node. The other side of each half bridge is connected to the high speed crossbar switch in the preferred embodiment so that it can be connected to the other half bridges. The crossbar switch can be thought of as a stack of separate layers of separate high speed backplane data paths connecting all the half bridges together by way of a switching network between the high speed backplane data path layers. The switching network functions to establish selective connections between layers and can be controlled such that any bridge on any layer can talk to any other bridge on any other layer. This allows multiple concurrent connections across the switch between a plurality of pairs of source nodes on one loop and a plurality of pairs of destination nodes on other loops or source and destination nodes coupled individually to half bridges. The switch architecture allows simultaneous purely local loop tenancies on any FCAL net coupled to any particular half bridge so long as another node on the FCAL net is not involved in a loop tenancy which involves communication across the switch from one port on one FCAL net to another port on another FCAL net.
Flow control using the OPN primitive only to establish connections across the switch is used to eliminate the need for large amounts of memory. As a result, the switch is capable of operating at a high throughput rate, but neither the half bridges nor the crossbar switches has the amount of memory of an FL_port of a fabric switch that would be required to make the fabric switch capable of operating at the same throughput rate.
Another significant advantage of the invention is that the nodes on the individual FCAL nets can be conventional NL node designs which already exist. An NL node is a node on an FCAL net which understands and can implement the FCAL flow controlled loop connection protocol between source and destination nodes to transfer data using OPN, RRDY and CLS primitives and large data frames. Because the embodiments of the switches described herein are all compatible with conventional NL nodes, the genus of switches described herein has the advantage that when the network is upgraded, only the switch needs to be upgraded and all the nodes can remain the same thereby saving substantial expense to the customer.
Dual simplex capability is also taught to improve the throughput of any network of FCAL nets coupled by any type of switch. Dual simplex capability allows a source node on a first FCAL net which is transmitting data on a front channel connection to a destination node on a second FCAL net through a switch connection to simultaneously receive data via a back channel connection from a third node on a third FCAL net. This is advantageous to improve throughput because in many cases, destination nodes to which data has been transmitted have no data to transmit back to the source node that sent them the data while other nodes do have data to be transmitted to the source node.
Dual simplex capability is accomplished in all species within the genus of the invention to further increase throughput. It is accomplished by three basic steps, illustrated in FIG. 15:
1) establishing a front channel half duplex data path between a source node and destination node on different FCAL nets (step 350) and stripping and storing or counting any buffer credit RRDY primitives output by the source node and not transmitting them to the destination node (step 352);
2) establishing a back channel data path between a third node and said source node but not transmitting to said source node any OPN primitive emitted by said third node (step 354), and transmitting a number of RRDYs either equal to the number of RRDYs output by said source node or the number of RRDYs needed by said third node to send all the data it has to said source node before closing said back channel connection (step 356), transmission of said RRDYs being one at a timexe2x80x94any excess RRDYs not used by the third node are saved for use by another third node in a subsequent dual simplex back channel connection; and
3) receiving any RRDYs transmitted by said destination node and mixing them in with data frames and/or primitives transmitted on the back channel by the third node so as to exercise flow control on transmissions of data frames from the source node to said destination node; (step 358).